1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Related Background Art
Along with the progress of microminiaturization of DRAMs and other semiconductor storage devices, coupling capacitance of bit line pairs is getting greater and greater. Increase of the coupling capacitance invites interference when data stored in the memory cell is amplified. Conventionally, in order to prevent noise caused by the interference, semiconductor storage devices have been configured to disconnect the bit lines from the sense amplifier when amplifying data after reading the data from the memory cell.
FIG. 21 is a circuit diagram of an amplifier circuit 10 provided in a conventional semiconductor storage device. FIG. 21 illustrates a memory cell 11 on the left and a memory cell 12 on the right. One line of a bit line pair BLL/bBLL is connected to the memory cell 11. One line of a bit line pair BLR/bBLR is connected to the memory cell 12. A bit line pair BLS/bBLS is connected to a sense amplifier in the amplifier circuit 10. The bit line pair BLL/bBLL is connected to bit line pair BLS/bBLS via transistors Q9 and Q10. The bit line pair BLR/bBLR is connected to the bit line pair BLS/bBLS via transistors Q11 and Q12.
Transistors Q9 and Q10 are controlled by a control signal ΦL, and transistors Q12 and Q11 are controlled by a control signal ΦR. If the memory cell 11 has been selected, transistors Q12 and Q11 are switched OFF. As a result, the bit line pair BLS/bBLS is disconnected from the bit line pair BLR/bBLR. If the memory cell 12 has been selected, transistors Q9 and Q10 are switched OFF. As a result, the bit line pair BLS/bBLS is disconnected from the bit line pair BLL/bBLL. Disconnection of the bit line pair BLS/bBLS from the bit line pair BLR/bBLR or BLL/bBLL results in isolating the capacitance of the bit line pair BLR/bBLR or BLL/bBLL in the memory cell array CA from the bit line pair BLS/bBLS in the amplifier circuit 10.
A precharge circuit 15 in the amplifier circuit 10 precharges the respective bit line pairs BLL/bBLL, BLR/bBLR and BLS/bBLS to Vref before the memory cell 11 or 12 is selected. The sense amplifier amplifies data from the memory cell 11 or 12.
FIG. 22 is a circuit diagram of a control circuit 20 that applies the control signal ΦL to the amplifier circuit 10 shown in FIG. 21. The control circuit 20 can output one of voltage values Vpp, Vdd, Vii or Vss.
A boost signal BOOST-L turns a P-channel transistor Q39 ON and can thereby raise the voltage of the control signal ΦL to Vpp. Vpp is a voltage value of the control signal ΦL, which renders the transistors Q9 and Q10 a higher drive power state, and it is higher than Vdd.
An isolating signal bISO-L turns a P-channel transistor Q35 On via a NAND gate G14, and can thereby adjust the voltage of the control signal ΦL to Vdd. Vdd is a voltage value of the control signal ΦL during the precharge of the bit line pairs BLL/bBLL, BLR/bBLR and BLS/bBLS.
In addition, the isolation signal bISO-L turns an N-channel transistor Q36 ON via a NOR gate G16, and can thereby adjust the voltage of the control signal ΦL to Vii. Vii is a voltage value that turns the transistors Q9 and Q10 OFF. Vii is higher than Vss and lower than Vdd.
A select signal SEL-R turns an N-channel transistor Q34 ON and can thereby adjust the control signal ΦL to Vss. Vss is the ground voltage. In addition, the select signal SEL-R controls a switch composed of a P-channel transistor Q31 and an N-channel transistor Q32. Thereby, a signal bBOOST-L, which is the inverted signal of the boost signal BOOST-L, is input to the NAND gate 14, and the boost signal BOOST-L is input to the NOR gate G16. The select signal SEL-R is HIGH when selecting the memory cell 12 shown in FIG. 21, and LOW when selecting the memory cell 11 shown in FIG. 21.
FIG. 23 is timing chart that shows operations of amplifier circuit 10 shown in FIG. 21 and the control circuit 20 shown in FIG. 22. With reference to FIG. 23, performance of the amplifier circuit 10 when amplifying data of the memory cell 11 will be explained. Before the amplifier circuit 10 reads out data, voltage of the control signal ΦL and ΦR are Vdd. Therefore, transistors Q9, Q10, Q12 and Q11 are ON.
First, the precharge signal EQ is set LOW to turn the precharge circuit 15 OFF (point of time to). At this time, in response to the control signal ΦR being set to Vss, the transistors Q11 and Q12 are turned OFF. As a result, the memory cell 12 is isolated from the amplifier circuit 10.
Subsequently, the word line WLL is set HIGH to turn the N-channel transistor Q1 ON (time t1). Thereby, the sense amplifier 16 receives data of the memory cell 11. That is, the data of the memory cell 11 is applied to the bit line pairs BLS/bBLS.
Next, the isolating signal bISO-L is set LOW to turn the transistor Q35 OFF and turn the transistor Q36 ON (time t2). Thereby, the voltage Vii is applied to the amplifier 10 in lieu of Vdd as the control signal ΦL. Since the voltage of the control signal ΦL changes from Vdd to Vii, the transistors Q9 and Q10 shown in FIG. 21 are switched OFF.
After that, the sense amplifier 16 amplifies data of the memory cell 11. After the data is amplified, the boost signal BOOST-L is set HIGH (time t3). Then, the P-channel transistor Q39 switches ON, and the voltage of the control signal ΦL rises to Vpp. As a result, the transistors Q9, Q10 shown in FIG. 21 again turn ON, and amplified data is again written in the memory cell 11. Since the control signal ΦL changes to Vpp higher than Vdd, sufficient charge can be accumulated in the capacitor C1.
Subsequently, the word line WLL is set LOW (time T4).
Further, by setting the isolating signal bISO-L HIGH and the boost signal BOOST-L LOW, the control signals ΦL and ΦR are returned to Vdd (time T5). As a result, the transistors Q9 and Q10 maintain the ON states, and the transistors Q11 and Q12 change to the ON states. Simultaneously, by setting the precharge signal EQ HIGH, the bit line pairs BLL/bBLL, BLR/bBLR and BLS/bBLS are precharged.
In the conventional technique introduced above, in response to the change of the control signal ΦL to Vii, the bit line pair BLS/bBLS is isolated from the bit line pair BLL/bBLL. As a result, while the sense amplifier 16 amplifies data, noise caused by the coupling capacitance of the bit lines pair BLL/bBLL is prevented. Moreover, since the sense amplifier 16 is sufficient to amplify the potential difference between the bit lines of the bit line pair BLS/bBLS, it can amplify data quickly.
However, since this technique writes data in the memory cell again, the sense amplifier 16 has to amplify the potential difference between the bit lines of the bit line pair BLL/bBLL similarly to the bit line pair BLS/bBLS after it amplifies data in the bit line pair BLS/bBLS. The point of time where the sense amplifier 16 starts amplification of the potential difference of the bit line pair BLL/bBLL is the time t3 where the control signal ΦL rises to Vpp.
At that time, since the control signal ΦL is rapidly amplified from Vii to Vpp, the transistors Q9, Q10 immediately change to the ON states. As a result, capacitance of the bit line pair BLL/bBLL is suddenly added to the capacitance of the bit line pair BLS/bBLS. As a result, the voltage of the bit line bBLS amplified to the HIGH level lowers due to the connection to the bit line bBLL. On the other hand, the voltage of the bit line BLS amplified to the LOW level rises due to the connection to the bit line BLL. That is, noise occurs in the bit line pair BLS/bBLS.
The noise may undesirably reverse the potential difference between the bit lines bBLS and BLS, which leads to false recognition of data.